Hello, I'm Yichen Yang, a second year Ph.D student at the Circuits and Architecture Design Research (CADRe) group within University of Michigan in Computer Science and Engineering, advised by Prof. Ronald Dreslinski. My research interest lies in computer architecture and hardware accelerators.

[Email] [CV] [Google Scholar] [Github] [Linkedin]


  • Prodigy received the best paper award @HPCA2021!
  • I will start an internship at Apple CPU Design &Verification team in Summer 2021!
  • MISC

  • I have many genius friends and this Link will redirect you to one of them.
  • Publication

    Prodigy: Improving the Memory Latency of Data-indirect Irregular Workloads using Hardware/Software Co-design

    IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, Best Paper Award

    Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi, Todd Austin, Michael O'Boyle, Scott Mahlke, Trevor Mudge, Ronald Drelinski.
    [Paper] [Slides] [Full Presentation] [Short Presentation] [BibTex] [DOI] [Best Paper Award]

    CoPTA: Contiguous Pattern Speculating TLB Architecture

    International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2020

    Yichen Yang, Haojie Ye, Yuhan Chen, Xueyang Liu, Nishil Talati, Xin He, Trevor Mudge, Ronald Dreslinski
    [Paper] [Slides] [BibTex] [DOI]

    Parallelism Analysis of Prominent Desktop Applications - An 18-Year Perspective

    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019

    Siying Feng, Subhankar Pal, Yichen Yang, Ronald Dreslinski
    [Paper] [Slides] [Github] [BibTex] [DOI]


    Hardware-Software Co-Designed Cache Bypass Mechanism on X86 Machine

    EECS 583 - Advanced Compilers Research Project

    Yichen Yang, Wentao Zhang, Wenqi Zhu, Zhiyi Pan

    In this project, we build an end-to-end HW-SW co-designed tool chain including compiler and hardware simulator modification to show that cache bypass brings performance gains to X86 machine under some circumstances.
    [Report] [Slides]

    Understanding Indoor 3D Geometry from AmbientSounds

    EECS 545 Machine Learning Research Project

    Xixi Hu, Ziyang Chen, Linyi Jin, Yichen Yang

    In this project, we demonstrate ambient sounds are able to perform these tasks under certain constraints, and analyze representative failure cases. Additionally, we show we can train a comparable model using visual depth estimation as pseudo-labels.

    Transmuter: Efficient General-Purpose Acceleration via Reconfiguration and Spatial Dataflow

    EECS 570 Parallel Computer Architecture Research Project

    Sung Kim, Kyle May, Chi-Sheng Yang, Yichen Yang, Yuhan Chen,

    Transmuter is a general-purpose accelerator design composed of light-weight cores and reconfigurable interconnects and memories. Through simple hardware reconfiguration mechanisms, Transmuter achieves state-of-theart efficiency on diverse kernels with disparate compute and data movement patterns.
    [Full Paper]

    Text & Vision-Fused Framework for Academic Paper Review

    EECS 498/598 Deep Learning Final Project

    Yichen Yang, Tongan Cai, Shuyang Huang, Jiachen Liu

    We implemented a Text & Vision-Fused deep learning model, which can act as a pre-selector for academic paper review.
    [Report] [Poster]

    2-Way Superscalar R10K Style Out-of-Order Processor

    EECS 470 Computer Architecture Final Project

    Yichen Yang, Yuhan Chen, Zixuan Li, Haiyang Jiang, Tian Pang

    We implemented 2-way superscalar, R10K style out-of-order processor with System Verilog, including plenty of advanced features to improve the performance.

    Stacked L-TAGE & Tournament Branch Predictor

    Undergraduate Research Project

    Yichen Yang, Fang Han, Sam Schiferl, Ronald Dreslinski

    We implemented a stack structure to the global history register (GHR) of an L-TAGE and a Tournament branch predictor to achieve a per-function history register with gem5 simulator.

    Single-view Surface Normal Prediction

    EECS442 Computer Vision Final Project

    Shengyi Qian, Linyi Jin, Yichen Yang

    We developed a machine learning model using stacked hourglass ConvNet to predict the surface normal of a object from a single view image, and broke the record from last year.
    [Slide] [Github]


    EECS 470 - Computer Architecture Instructional Aide
    Winter 2019

    VG 100 - Intro. to Engineering Teaching Assistant
    Summer 2017


    University of Michigan - Ann Arbor
    2019.9 - 2024.5 (Expected)

    Ph.D. in Computer Science and Engineering, GPA: 4.00/4.00

    Advised by Ronald Dreslinski

    University of Michigan - Ann Arbor
    2017.9 - 2019.5

    B.S.E. in Computer Engineering, major GPA: 3.91/4.00

    Shanghai Jiao Tong University (UM-SJTU Joint Institute)
    2015.9 - 2019.8

    B.S.E. in Electrical and Computer Engineering, major GPA: 3.70/4.00