Hello, I'm Yichen Yang, a first year Ph.D student at the Circuits and Architecture Design Research (CADRe) group within University of Michigan in Computer Science and Engineering, advised by Prof. Ronald Dreslinski. My research interest lies in computer architecture and hardware accelerators.

[Email] [CV] [Google Scholar] [Github] [Linkedin]


  • Back to Ann Arbor and join Cadre lab, adviced by Prof. Ronald Dreslinski!
  • MISC

  • I have many genius friends and this Link will redirect you to one of them.
  • Research

    Parallelism Analysis of Prominent Desktop Applications - An 18-Year Perspective

    Siying Feng, Subhankar Pal, Yichen Yang, Ronald Dreslinski

    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019

    We performed extensive analysis of the parallelism exploited by modern software on a state-of-the-art desktop machine and compared against analyses from 2000 and 2010.
    [Paper] [Slides] [BibTex] [Github]

    Stacked L-TAGE & Tournament Branch Predictor

    Yichen Yang, Fang Han, Sam Schiferl, Ronald Dreslinski

    We implemented a stack structure to the global history register (GHR) of an L-TAGE and a Tournament branch predictor to achieve a per-function history register with gem5 simulator.

    Course Projects

    Transmuter: Efficient General-Purpose Acceleration via Reconfiguration and Spatial Dataflow

    Sung Kim, Kyle May, Chi-Sheng Yang, Yichen Yang, Yuhan Chen

    EECS 570 Parallel Computer Architecture Research Project

    Transmuter is a general-purpose accelerator design composed of light-weight cores and reconfigurable interconnects and memories. Through simple hardware reconfiguration mechanisms, Transmuter achieves state-of-theart efficiency on diverse kernels with disparate compute and data movement patterns.
    [Report] [Poster]

    Text & Vision-Fused Framework for Academic Paper Review

    Yichen Yang, Tongan Cai, Shuyang Huang, Jiachen Liu

    EECS 498/598 Deep Learning Final Project

    We implemented a Text & Vision-Fused deep learning model, which can act as a pre-selector for academic paper review.
    [Report] [Poster] [Github]

    2-Way Superscalar R10K Style Out-of-Order Processor

    Yichen Yang, Yuhan Chen, Zixuan Li, Haiyang Jiang, Tian Pang

    EECS 470 Computer Architecture Final Project

    We implemented 2-way superscalar, R10K style out-of-order processor with System Verilog, including plenty of advanced features to improve the performance.

    Single-view Surface Normal Prediction

    Shengyi Qian, Linyi Jin, Yichen Yang

    EECS442 Computer Vision Final Project

    We developed a machine learning model using stacked hourglass ConvNet to predict the surface normal of a object from a single view image, and broke the record from last year.
    [Slide] [Github]


    EECS 470 - Computer Architecture Instructional Aide
    Winter 2019

    VG 100 - Intro. to Engineering Teaching Assistant
    Summer 2017


    University of Michigan - Ann Arbor
    2019.9 - 2024.5 (Expected)

    Ph.D. in Computer Science and Engineering

    University of Michigan - Ann Arbor
    2017.9 - 2019.5

    B.S.E. in Computer Engineering, major GPA: 3.91/4.00

    Shanghai Jiao Tong University (UM-SJTU Joint Institute)
    2015.9 - 2019.8

    B.S.E. in Electrical and Computer Engineering, major GPA: 3.70/4.00